1. Field of the Disclosure
The present disclosure relates generally to integrated circuit (IC) fabrication and packaging.
2. Description of the Related Art
Conventionally, integrated circuit fabrication involves back-end-of-line (BEOL) processing in which the active elements and other circuit components formed at the active surface of a die substrate are interconnected (or “wired”) via a metal interconnect structure formed at a plurality of metal layers overlying the active surface of the die substrate. The resulting die typically is then tested through probing of pads formed at or above the top metal layer. However, because of the coarser pitch of the pads and other features at the top metal layers, the probe testing often is limited in its scope.
The probe testing of a die may reveal that one or more components of the die are inoperative (that is, either fully non-operational or operating outside of acceptable parameters). In some instances, such die are discarded. However, in other instances, the die can be binned as a lower-performance part by de-powering the inoperative component. Typically, the component is de-powered using on-die power switching circuits that re-route supply voltages from the component. This de-powering approach also is frequently taken to provide multiple versions of a product from the same design, whereby the feature set of a particular version may be implemented by de-powering circuitry not used in the feature set for the version. However, the on-die power switching circuits conventionally used to provide de-power options typically are also present in the power supply paths of the functioning circuitry. As these power switching circuits consume power and reduce the operating voltage supplied to the functioning circuitry, they can degrade the performance of the functioning circuitry and reduce the overall power efficiency of the IC device implementing the die.